The present invention relates to a switched capacitor circuit applicable to various types of analog circuit such as a high precision low-pass filter, an A/D converter and a D/A converter and, more particularly, to a switched capacitor circuit which comprises a MOS integrated circuits.
A switched capacitor circuit basically comprises: an operational amplifier; a sampling circuit having two analog switches which are alternately turned on/off in accordance with sampling clocks; and a capacitor which is alternately connected to a signal input and an inverting input of the operational amplifier in accordance with the on/off operation of the analog switches so as to transfer a charge corresponding to an input voltage by charging/discharging; and an integrating capacitor connected between an output of the operational amplifier and the inverting input thereof so as to integrate an input signal.
When the switched capacitor circuit of the type described above comprises a CMOS device, parasitic capacitances are present in the gate-source path and the gate-drain path of an input transistor of the operational amplifier. When power supply voltages (V.sub.DD, V.sub.SS) applied to the operational amplifier vary, the source or drain voltage of the input transistor varies, so that charge flows through the parasitic capacitance (i.e., an input capacitance of the operational amplifier) to an imaginary ground point of the inverting input of the operational amplifier. This charge is then integrated by the integrating capacitor.
A change in power supply voltage (i.e., power supply noise) is transmitted by the input capacitance of the operational amplifier to a signal line of the switched capacitor circuit, thereby degrading the signal-to-noise (S/N) ratio. In other words, a power supply rejection ratio (PSRR) is degraded. Leakage of power supply noise by the input capacitance to the signal line is a first cause of degradation of the electrical characteristics of the switched capacitor circuit.
The two analog switches comprise a PMOS and an NMOS, respectively. Parasitic capacitances are present in the gate-source path and the gate-drain path of the PMOS, the path between the source of the PMOS and an N-substrate, and the path between the drain thereof and the N-substrate. Similarly, parasitic capacitances are present in the gate-source path and the gate-drain path of the NMOS, the path between the source thereof and a P-well region, and the path between the drain thereof and the P-well region. A clock of a power supply voltage is applied to the gates of the NMOS and PMOS so as to turn on/off the corresponding analog switches. When this power supply voltage varies, charge flows to the imaginary ground point of the operational amplifier through the parasitic capacitances. This charge is integrated by the integrating capacitive element. This is a second cause of degradation of the power supply rejection ratio of the switched capacitor circuit.
Since the parasitic capacitance is present in any other device as well as the MOS device, the same problem occurs even if the switched capacitor circuit comprises any device other than the MOS device.
Power supply noise components include the following noise components. First, noise occurs in a power supply itself: in particular, a 100-kHz clock leaks in a switching regulator. Second, the power supply voltage varies in accordance with the operation of logic circuits on a single chip. Third, noise occurs as crosstalk from peripheral logic LSIs. These noise components are generated in a wide frequency bandwidth. For example, when a PCM-CODEC LSI is used, many power supply noise components are present since a compact built-in power source is used and 1k-gate logic circuits are integrated on a single chip.
Furthermore, since an analog signal is sampled with a switching frequency, a high-frequency component which is higher than the switching frequency causes aliasing to fall below the switching frequency. For this reason, the high-frequency component is superposed on a signal in a signal range which corresponds to an actual noise range.
As described above, the power supply noise components are present in a wide frequency bandwidth. Furthermore, the power supply noise components leak to the signal line through the parasitic capacitances. As a result, a high-performance switched capacitor circuit cannot be obtained.
In order to eliminate the first cause of degradation of the switched capacitor circuit, a method is proposed for forming an on-chip circuit for regulating the negative power supply voltage (Harlan Ohara et al., "A Precision Low-Power PCM Channel Filter with On Chip Power Supply Regulation", IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 6, December 1980, PP. 1005-1013). According to this method, since a power supply circuit is regulated, a large-sized transistor is required and high power is required to regulate the power supply voltage in a wide frequency range. Furthermore, since the voltage regulator is arranged between the power supply and the amplifier, the signal magnitude is slightly decreased, resulting in inconvenience.
In order to eliminate the second cause of degradation of the switched capacitor circuit, a method is proposed wherein a P-well layer is formed between a MOS switch and a substrate and the P-well layer is biased by a regulated voltage (Douglas G. Marsh et al., "A Single-Chip CMOS PCM Codec with Filters", IEEE Journal of Solid-State Circuits, Vol. SC-16, No. 4, August 1981, PP. 308-315). This method has advantages in having a compact circuit architecture and low power dissipation. However, this method can only be applied for an NMOS transistor, so the signal magnitude is limited as compared with the case of a CMOS. Furthermore, since this method disables elimination of the power supply noise components transmitted through the input capacitance of the operational amplifier and the gate capacitance of the switch, a great improvement in the power supply rejection ratio cannot be expected.